1. Field of the Invention
This invention relates generally to the manufacture of semiconductor devices, and more particularly to a method for improving the resistance of photoresist against metal etch plasma.
2. Description of the Related Art
Since the introduction of semiconductor devices, the size of semiconductor devices have been continuously shrinking, resulting in smaller semiconductor chip size and increased device density on the chip. In fabricating smaller semiconductor devices, etch process is an important semiconductor process since it defines line-widths and other micro features on integrated circuits. For example, a metal etch process is widely used to etch metal layers, such as aluminum and aluminum alloy layers, that are used to form interconnect lines and contacts.
With the continuing need to increase in integrated circuit density, one of the main problems in etching metal films is the decreasing size of a photoresist mask. Specifically, fabricating a higher resolution integrated circuit chip requires a higher resolution photomask with thinner photoresist layers. For example, the thickness of a photoresist layer, for approximately 1 micron technology devices, may be between 2 to 3 microns. In contrast, for 0.2 micron technology devices, the thickness of the photoresist may be reduced to about 0.6 micron. Since metal thickness is largely dependent on electrical resistance and electromigration requirements, the metal thickness typically does not scale with the photoresist thickness.
The use of thinner photoresist layers presents several problems in the metal etching process. For example, photoresist layers are often prematurely consumed during plasma etching of metal films. As is well known, dry etching processes such as sputter etching, reactive-ion etching, and plasma etching, are widely used in etching metals. This is because dry etching increases interconnect capabilities by providing highly anisotropic etching profiles.
On the other hand, dry etching processes also typically produce undesirable facets on the surfaces of a photoresist layer of Prior Art FIG. 1, which illustrates a cross section of a silicon wafer stack 100 after being exposed to bombarding etchant ions in a metal etching process. The wafer stack 100 includes a substrate 102, an oxide (e.g., IMO) layer 104, a metallization layer 106, and a photoresist layer 108. The oxide layer 104 is deposited on the substrate 102. The metallization layer 106 is formed over the oxide layer 104 and includes aluminum or aluminum alloys. The patterned and etched photoresist layer 108 includes photoresist portions 118, 120, 122, and 124 formed on metallization layer portions 110, 112, 113, and 116, respectively, of the metallization layer 106.
In this wafer stack configuration, etchant ions designed to etch metals (e.g., Cl.sub.2, BCl.sub.3, etc.) have also bombarded and etched the exposed surfaces of the photoresist layer to form a plurality of facets 126, 128, 130, 132, 134, 134, 138, and 140 on the photoresist portions 118, 120, 122, and 124. The facets 126, 128, 130, 132, 134, 134, 138, and 140 typically result from bombardment of etchant ions. More specifically, in dry etching processes, etchant ions are used to bombard the surface of a metallization layer in order to remove the metallization layer from those regions not covered by photoresist. These etchant ions generally have sufficient energy to sputter the relatively soft photoresist material. Sputtering erodes the photoresist and creates a facet at an angle of approximately 45 degrees to the incoming ions because sputter yield is maximum at this angle.
With continuing reference to Prior Art FIG. 1, the faceting of the photoresist layer portions 118, 120, 122, and 124 may subsequently lead to the complete removal of the photoresist layer 108 and also result in removal of portions of the metallization layer 106. When this happens, unwanted open or short circuits may be produced. In particular, when the facet etches down and breaks through to the underlying metallization layer, a phenomenon commonly known as "etch mask failure" occurs and the etch mask will no longer function as intended. For example, the faceted features of the photoresist layer portions 120 and 124 expose the sides 142, 144, 146, and 148 of the metallization layer portions 112 and 116. These cases demonstrate etch mask failures, which refer to the exposure of the metal portions 110, 112, 114, and 116 under the photoresist layer 106. When an etch mask failure occurs, the exposed metal portions 110, 112, 114, and 116 will unfortunately be etched away. Etch mask failures are undesirable because they may cause circuit failures and adversely affect subsequent semiconductor processes that are carried out for subsequent layers that may be fabricated above the metallization layer.
In view of the foregoing, what is needed is a method for reducing the faceting effect of photoresist layers during subsequent metal etch processes.